In　order　to　meet　the　stringent　requirements　of　high　speed　time-interleaved　sampling　for　clock,　we　take　a　low　phase　noise　clock　chip　AD9522　with　an　internal　integrated　2　GHz　VCO　(voltage　controlled　oscillator)　to　provide　four　sampling　clocks　with　a　phase　difference　of　90°　and　a　frequency　of　250　MHz　for　four　alternately　sampled　analog-to-digital　converters.　Based　on　the　introduction　of　the　characteristics　of　AD9522,　the　design　of　the　sampling　clock　circuit　and　the　calculation　of　the　parameters　of　the　loop　filter　are　described　in　detail.　The　relevant　software　simulation　is　used　to　show　that　the　design　meets　the　system　requirements.　©　2019　IEEE.