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作者:

Li, Zefa (Li, Zefa.) | Wang, Hui (Wang, Hui.) | Wang, Wensi (Wang, Wensi.) | Chen, Zhijie (Chen, Zhijie.) | Wan, Peiyuan (Wan, Peiyuan.)

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EI

摘要:

This paper describes the basic principle of the gated clock. In the system design phase, the gated clock is added to the RTL code for low-power design. Under TSMC 350 nm CMOS process, Synopsys' Design Compiler, IC Compiler, PT and other tools were used to complete the back-end physical implementation. The total power consumption of the uninserted gated clock is 111.98}\\mathbf{μ W}$, the total power consumption of the inserted gated clock is 84.83\μ W}$, the total power consumption is reduced by 24.25%, and the area is also reduced. © 2019 IEEE.

关键词:

Clocks Electric power supplies to apparatus Electric power utilization Program compilers

作者机构:

  • [ 1 ] [Li, Zefa]Beijing Embedded System Key Lab, College of Microelectronics, Faculty of Information Technology, Beijing University of Technology, Beijing, China
  • [ 2 ] [Wang, Hui]Beijing Smartchip Microelectronics Technology Company Limited, Beijing, China
  • [ 3 ] [Wang, Wensi]Beijing Embedded System Key Lab, College of Microelectronics, Faculty of Information Technology, Beijing University of Technology, Beijing, China
  • [ 4 ] [Chen, Zhijie]Beijing Embedded System Key Lab, College of Microelectronics, Faculty of Information Technology, Beijing University of Technology, Beijing, China
  • [ 5 ] [Wan, Peiyuan]Beijing Embedded System Key Lab, College of Microelectronics, Faculty of Information Technology, Beijing University of Technology, Beijing, China

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ISSN: 2163-5048

年份: 2019

卷: 2019-October

页码: 27-30

语种: 英文

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