The　digital　low-dropout　regulator　is　appropriate　for　the　digital　circuits　for　its　low-voltage　and　low-power　design.　However,　the　digital　LDOs　suffer　an　output　voltage　ripple　caused　by　the　limit　cycle　oscillation　and　its　accuracy　needs　to　be　improved.　This　paper　presents　a　limit　cycle　oscillation　reduction　technique　for　the　digital　LDOs　to　suppress　the　output　voltage　ripple.　The　proposed　technique　uses　a　two-stage　regulation　method　to　add　a　fine　MOSFETs　array　and　a　second-stage　barrel　shifter　to　the　traditional　digital　LDOs.　The　simulation　results　show　that　the　proposed　technique　reduces　the　output　voltage　ripple　from　3.72　mV　to　0.49　mV　on　the　average　and　the　regulation　accuracy　is　improved　about　8　times.　©　2019　IEEE.