An Arithmetic Unit and Multiplying Accumulation Unit of a Custom Floating Point Data Format - 文章详情页

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EI Scopus

摘要：

In　this　paper,　a　floating　point　multiplication　and　accumulation　operator　based　on　FPGA　is　designed　for　neural　network　calculation,　and　a　custom　32　bit　floating-point　data　format　is　used　to　change　the　amount　of　computation　by　changing　the　overall　structure　of　the　data,　and　the　performance　of　the　operator　is　optimized.　Finally,　the　simulation　results　in　FPGA　are　given　to　verify　the　correctness　of　the　design.　The　design　saves　the　resources　by　comparing　the　floating　point　operation　with　the　common　algorithm　of　32　bit　floating-point　data　of　the　IEEE　standard.　©　2018　IEEE.

关键词：

Integrated circuit design Field programmable gate arrays (FPGA) Microsystems IEEE Standards Digital arithmetic Integrated circuits

作者机构：

[ 1 ] [Lv, Ang]Beijing University of Technology, College of Microelectronics, Beijing, China
[ 2 ] [Wang, Chao]Beijing University of Technology, College of Microelectronics, Beijing, China
[ 3 ] [Hou, Ligang]Beijing University of Technology, College of Microelectronics, Beijing, China
[ 4 ] [Zeng, Zhiyong]Beijing University of Technology, College of Microelectronics, Beijing, China
[ 5 ] [Guo, Jia]Beijing University of Technology, College of Microelectronics, Beijing, China
[ 6 ] [Jiang, Nan]Beijing University of Technology, College of Microelectronics, Beijing, China

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查看成果更多字段

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2018，3rd IEEE International Conference on Integrated Circuits and Microsystems, ICICM 2018
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2012，2012 International Conference on Industrial Control and Electronics Engineering, ICICEE 2012
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2003，IEEE Systems, Man and Cybernetics Society Information Assurance Workshop
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2018，12th IEEE International Conference on Anti-Counterfeiting, Security, and Identification, ASID 2018

来源：

年份： 2018

页码： 282-285

语种：英文

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SCOPUS被引频次： 1

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归属院系：

信息学部电子科学与技术学院（微电子学院）

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