Impact of Gate Asymmetry on Gate-All-Around Silicon Nanowire Transistor Parasitic Capacitance - Details

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Abstract：

In　this　paper,　an　analytical　model　is　developed　for　parasitic　gate　capacitance　of　the　gate-all-around　(GAA)　silicon　nanowire　MOSFETs　(SNWT)　with　asymmetrical　top　and　bottom　gates.　The　modeling　results　show　that　the　gate-to-source/drain　spacer　significantly　impacts　on　the　parasitic　capacitance　especially　in　the　case　of　top-to-bottom　gate　misalignment.　It　is　found　that　the　optimized　top-to-bottom　gate　misalignment　may　achieve　smaller　Cp/Ctotal　so　as　to　improve　the　AC　performance　of　GAA　SNWT.　The　developed　capacitance　model　is　more　suitable　for　the　actual　process　for　further　device　design　optimization.　©　2018　IEEE.

Keyword：

Alignment Capacitance Silicon Nanowires MOSFET devices Integrated circuits

Author Community：

[ 1 ] [Dong, Xiaoqiao]Faculty of Information Technology, Beijing University of Technology, Beijing; 100124, China
[ 2 ] [Dong, Xiaoqiao]Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics, Peking University, Beijing; 100871, China
[ 3 ] [Yang, Yuancheng]Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics, Peking University, Beijing; 100871, China
[ 4 ] [Chen, Gong]Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics, Peking University, Beijing; 100871, China
[ 5 ] [Sun, Shuang]Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics, Peking University, Beijing; 100871, China
[ 6 ] [Cai, Qifeng]Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics, Peking University, Beijing; 100871, China
[ 7 ] [Li, Xiaokang]Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics, Peking University, Beijing; 100871, China
[ 8 ] [An, Xia]Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics, Peking University, Beijing; 100871, China
[ 9 ] [Xu, Xiaoyan]Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics, Peking University, Beijing; 100871, China
[ 10 ] [Zhang, Wanrong]Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics, Peking University, Beijing; 100871, China
[ 11 ] [Li, Ming]Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics, Peking University, Beijing; 100871, China

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Year： 2018

Language： English

Cited Count：

WoS CC Cited Count： 0

SCOPUS Cited Count： 4

ESI Highly Cited Papers on the List： 0 Unfold All

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Chinese Cited Count：

30 Days PV： 0

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信息学部

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