Design of the printed circuit board for board level drop impact base on the JEDEC standard - 文章详情页

作者：

Gu, Jian (Gu, Jian.) | Lei, Yongping (Lei, Yongping.) (学者：雷永平) | Lin, Jian (Lin, Jian.) | Fu, Hanguang (Fu, Hanguang.) (学者：符寒光) | Wu, Zhongwei (Wu, Zhongwei.)

收录：

EI Scopus

摘要：

the　reliability　of　solder　joint　under　drop　impact　is　a　crucial　research　area　due　to　the　smaller　and　higher　density.　The　test　standard　for　board　level　has　been　published　by　JEDEC　in　detail.　Based　on　JEDEC　board　level　drop　test　standard,　the　square　board　with　four　symmetry　component　is　designed　in　this　paper.　The　structure　size　of　test　board　is　0.5mm×121mm×121mm.　The　distance　of　the　center　component　to　the　center　of　test　board　is　15mm.　The　first　six　modal　frequency　is　23.56Hz,　136.37Hz,　138.53Hz,　165.98Hz,　346.35Hz　and　394.56Hz　respectively.　This　Design　benefits　for　the　board　level　drop　life　of　solder　joint　statistics　analysis.　And　the　0.5mm　thickness　design　can　be　used　as　replacement　test　board　to　analyze　the　failure　mechanism　of　solder　joint　under　relative　high　drop　impact　level.　©　2016　IEEE.

关键词：

Drops Electronics packaging Failure (mechanical) Printed circuit boards Printed circuit design Reliability Timing circuits

作者机构：

[ 1 ] [Gu, Jian]College of Materials Science and Engineering, Beijing University of Technology, Beijing, China
[ 2 ] [Lei, Yongping]College of Materials Science and Engineering, Beijing University of Technology, Beijing, China
[ 3 ] [Lin, Jian]College of Materials Science and Engineering, Beijing University of Technology, Beijing, China
[ 4 ] [Fu, Hanguang]College of Materials Science and Engineering, Beijing University of Technology, Beijing, China
[ 5 ] [Wu, Zhongwei]College of Materials Science and Engineering, Beijing University of Technology, Beijing, China

通讯作者信息：

电子邮件地址：

查看成果更多字段

成果类型
所属机构

所有年份指定年份从至