Calibration of timing mismatch in a two-channels time-interleaved ADC based on testing signal and its verification on FPGA - 文章详情页

作者：

Liu, Sujuan (Liu, Sujuan.) | Yang, Shishen (Yang, Shishen.) | Lv, Ning (Lv, Ning.)

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EI Scopus

摘要：

The　multi-channel　time-interleaved　analog-to-digital　converter　(TIADC)　makes　creating　high-resolution　and　high-speed　ADC　possible.　This　paper　adopts　a　known　low　frequency　sinusoidal　test　signal　and　the　FxLMS　algorithm　to　calibrate　the　timing　mismatches　in　a　two-channel　TIADC.　By　adopting　this　method,　the　timing　error　which　is　centralized　in　the　mid-frequency　band　can　be　easily　corrected.　This　calibration　algorithm　requires　a　slightly　oversampled　input　signal　to　produce　a　mismatch　band.　Through　the　numerical　simulation　in　MATLAB　and　the　measurement　on　a　FPGA　testing　board,　the　validity　of　this　calibration　technique　was　proved.　©　2016　IEEE.

关键词：

Analog to digital conversion MATLAB Field programmable gate arrays (FPGA) Timing circuits Calibration

作者机构：

[ 1 ] [Liu, Sujuan]College of Electronic Information and Control Engineering, Beijing University of Technology, Beijing; 100124, China
[ 2 ] [Yang, Shishen]College of Electronic Information and Control Engineering, Beijing University of Technology, Beijing; 100124, China
[ 3 ] [Lv, Ning]College of Electronic Information and Control Engineering, Beijing University of Technology, Beijing; 100124, China

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