In　three-dimensional　(3D)　integrated　circuit　(IC),　a　large　number　of　dummy　through　silicon　vias　(TSV)　are　required　for　thermal　and　thinning　concerns.　However,　limited　attention　is　paid　to　the　fact　that　these　dummy　TSVs　can　be　multi-functional　and　used　for　timing　purposes.　In　this　paper,　we　propose　to　use　those　＇timing　wasteful＇　dummy　TSVs　to　replace　bit　line　delay　cells.　Also,　a　TSV　allocation　algorithm　is　presented　to　optimize　the　TSV　array　layout.　Finally,　three　memory　designs　are　implemented　to　verify　the　feasibility　and　reliability　of　the　proposed　technology.　It　is　found　that　all　delay　cells　in　these　3　memories　can　be　replaced　by　TSV　arrays.　©　2016　IEEE.