Clock gating -A power optimization technique for smart card - 文章详情页

作者：

Zhou, Yongwang (Zhou, Yongwang.) | Peng, Xiaohong (Peng, Xiaohong.) | Hou, Ligang (Hou, Ligang.) | Wan, Peiyuan (Wan, Peiyuan.) | Lin, Pingfen (Lin, Pingfen.)

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EI Scopus

摘要：

Power　consumption　is　a　key　issue　of　smart　card　whose　power　is　supplied　by　induced　currents.　This　paper　has　described　the　principle　of　the　clock　gating　technology　which　is　used　to　optimize　power　consumption　of　the　smart　card　in　RTL　level.　It　turns　out　that　the　total　power　consumption　has　been　reduced　by　40%　using　the　proposed　method,　without　obvious　increase　in　area.　The　smart　card　using　the　clock　gating　technology　is　verified　and　tested　in　180nm　process.　©　2014　IEEE.

关键词：

Clocks Electric power utilization Smart cards

作者机构：

[ 1 ] [Zhou, Yongwang]Beijing Embedded System Key Lab, Beijing University of Technology, Beijing; 100124, China
[ 2 ] [Peng, Xiaohong]VLSI and System Lab, Beijing University of Technology, Beijing, China
[ 3 ] [Hou, Ligang]VLSI and System Lab, Beijing University of Technology, Beijing, China
[ 4 ] [Wan, Peiyuan]Beijing Embedded System Key Lab, Beijing University of Technology, Beijing; 100124, China
[ 5 ] [Lin, Pingfen]Beijing Embedded System Key Lab, Beijing University of Technology, Beijing; 100124, China

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