In　modern　High　Performance　Computing　(HPC)　Systems,　tens　to　hundreds　processing　units　are　integrated　on　a　single　chip,　which　lead　the　on-chip　interconnections　became　complicate　and　inefficiency.　The　traditional　NoC　designed　with　metallic　lines　face　serious　transmission　problems　as　the　computing　system　scales　up.　Emerging　interconnections　such　as　optical　interconnects　and　RF　Interconnects　(RF-I)　have　become　the　alternative　technologies.　The　hybrid　architectures　composed　with　traditional　RCs　and　emerging　interconnections　have　become　one　of　the　mainstreams　for　HPCs.　In　this　work　we　presented　a　new,　flexible　and　efficient　hierarchical　architecture　for　HPCs,　which　can　be　customized　according　different　applications　and　simply　implemented　with　traditional　2-D　mesh.　A　shared　RF-I　mechanism　is　applied　between　clusters　to　get　a　better　bandwidth　utilization,　and　an　efficient　hierarchical　mapping　approach　is　also　provided　along　with　the　proposed　architecture　to　both　shorten　the　communication　paths　for　frequently　communicated　nodes　and　long　distant　pairs　of　nodes.　Our　proposed　architecture　is　verified　through　the　extended　simulation　platform　with　cycle　accurate　simulation,　which　showed　that　our　architecture　is　able　to　reduce　average　flit　transmission　latency　by　an　average　of　19.5%　compared　to　the　recently　proposed　architecture　with　RF-I　shortcuts,　and　also　an　average　of　6.5%　improvement　of　energy　consumption　can　be　attained.　©　2014　WIT　Press.