Through-silicon　via　(TSV)　technology　has　been　the　core　of　the　next　generation　of　3D　integration.　Although　some　TSV　reliability　issues　have　been　addressed　in　some　literatures,　but　the　sidewall　scallop　resulted　from　Bosch　etch　process　has　not　been　thoroughly　investigated.　In　this　paper,　we　focus　on　the　effects　of　different　sidewall　scallops　on　the　interfacial　stress　evolution.　An　axi-symmetric　single　TSV　model　which　contains　three　interfaces　(Cu/Ta,　Ta/SiO2,　SiO2/Si)　is　taken　into　consideration.　Besides,　different　from　other　FEM　models　adopted　for　TSV　analysis,　the　roughness　factors　λ　and　h　are　employed　to　character　the　sidewall　scallop.　Based　on　the　FEM　results,　the　influence　of　geometric　parameters　such　as　the　thickness　of　Ta　layer　and　the　morphology　of　the　sidewall　scallop　are　investigated　to　develop　guidelines　for　TSV　design.　At　last,　the　equation　of　which　λ　and　h　should　be　satisfied　is　proposed,　and　provides　the　guidelines　for　Bosch　etch　process.　©　2014　IEEE.