To　test　and　optimize　brushless　dc　motor　(BLDCM)　controller,　a　hardware-in-the-loop　(HIL)　real　time　simulation　schematic　based　on　DSP　plus　FPGA　was　presented.　BLDCM　model　calculating　cycle　is　up　to　14us,　which　leads　to　the　motor　states　updating　at　least　one　motor　model　cycle　time　delay,　and　the　delay　will　result　to　accumulative　error.　To　pursue　an　accurate　and　fast　BLDCM　HIL　simulation　results,　a　new　interpolation　approach　was　proposed.　This　approach　is　processed　in　FPGA　and　parallel　computing　with　the　BLDCM　model　in　DSP.　During　BLDCM　model　cycle,　the　interpolation　method　is　used　to　improve　the　accuracy　by　changing　the　BLDCM　states　according　to　the　real　time　phase　voltage　signal.　In　view　of　the　nonlinear　dynamic　BLDCM　model,　a　lookup　table　of　BLDCM　parameters　obtained　from　static　finite　element　analyses　(FEA)　is　used.　By　using　the　method,　simulation　performance　under　disturbance　conditions　is　improved,　and　the　faster　computation　speed　is　obtained　while　keeping　the　same　high　precision　as　the　FEA　model.　©　2014　IEEE.