Novel CMOS SRAM voltage latched sense amplifiers design based on 65 nm technology - 文章详情页

作者：

Wei, Zikui (Wei, Zikui.) | Peng, Xiaohong (Peng, Xiaohong.) | Wang, Jinhui (Wang, Jinhui.) | Yin, Haibin (Yin, Haibin.) | Gong, Na (Gong, Na.)

收录：

EI Scopus

摘要：

A　novel　voltage　latched　sense　amplifier　is　proposed　in　this　paper.　It　applies　a　self-closing　bit-line　module　technique,　which　makes　the　input　and　output　nodes　separated　to　optimize　sensing　delay　and　power　consumption.　Initially,　the　size　of　transistors　in　the　circuits　is　adjusted　to　speed　up　the　circuit　and　lower　the　power.　The　simulation　results　show　that　the　proposed　design　improves　sensing　when　smaller　bit-lines　difference　requires　for　full-swing　amplification　as　the　conventional　voltage　latched　sense　amplifier.　The　proposed　design　also　improves　power　efficiency　at　least　30%　as　compared　to　the　conventional　voltage　latched　sense　amplifier.　©　2014　IEEE.

关键词：

Integrated circuit design CMOS integrated circuits

作者机构：

[ 1 ] [Wei, Zikui]VLSI and System Lab, Beijing University of Technology, Beijing; 100124, China
[ 2 ] [Peng, Xiaohong]VLSI and System Lab, Beijing University of Technology, Beijing; 100124, China
[ 3 ] [Wang, Jinhui]VLSI and System Lab, Beijing University of Technology, Beijing; 100124, China
[ 4 ] [Yin, Haibin]VLSI and System Lab, Beijing University of Technology, Beijing; 100124, China
[ 5 ] [Gong, Na]Dept. of Electrical and Computer Engineering, North Dakota State University, ND; 58102, United States

通讯作者信息：

[wang, jinhui]vlsi and system lab, beijing university of technology, beijing; 100124, china

电子邮件地址：

wangjinhui@bjut.edu.cn

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