The　h.264　standard　adopts　an　effective　intra-frame　prediction　coding　algorithm　to　reduce　spatial　redundancies　and　improve　the　compression　ratio,　but　this　high　performance　was　reached　by　exhaustively　trying　all　available　prediction　modes　and　selecting　the　best　one,　which　becomes　the　bottleneck　of　this　algorithm.　In　this　paper,　we　propose　a　high　throughput　prediction　and　mode　decision　architecture　to　lessen　the　impact　of　this　part　to　the　h.264　coder.　The　architecture　was　described　in　Verilog　HDL　and　synthesized　to　Xilinx　Spartan6　FPGA,　the　results　show　it　gets　higher　throughput　when　compared　with　related　work.　©　2013　IEEE.