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作者:

Gong, Na (Gong, Na.) | Wang, Jinhui (Wang, Jinhui.) | Sridhar, Ramalingam (Sridhar, Ramalingam.)

收录:

EI Scopus

摘要:

In this paper, we propose an application-driven ALU design methodology to achieve high level of power efficiency for modern microprocessors. We introduce a PN selection algorithm (PNSA) which enables designers to select power efficient dynamic modules for different applications, based on the detailed analysis of dynamic circuits. Experimental results on ISCAS85 and 74X-Series benchmark circuits show that the power consumption of 8-bit ALU based on this approach can be reduced by 54%-60% for different frequency levels as compared to the conventional dynamic ALU design, demonstrating the effectiveness of the proposed method on application-driven custom ALU design. © 2013 IEEE.

关键词:

Benchmarking Delay circuits Integrated circuit design Logic circuits

作者机构:

  • [ 1 ] [Gong, Na]University at Buffalo, State University of New York, Buffalo, NY, United States
  • [ 2 ] [Wang, Jinhui]VLSI and System Lab, Beijing University of Technology, Beijing, China
  • [ 3 ] [Sridhar, Ramalingam]University at Buffalo, State University of New York, Buffalo, NY, United States

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来源 :

ISSN: 1948-3287

年份: 2013

页码: 185-188

语种: 英文

被引次数:

WoS核心集被引频次: 0

SCOPUS被引频次: 5

ESI高被引论文在榜: 0 展开所有

万方被引频次:

中文被引频次:

近30日浏览量: 3

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