In　this　paper,　we　present　a　partial-parallel　decoder　architecture　based　on　Min-Max　algorithm　for　quasi-cyclic　non-binary　LDPC　codes.　An　efficient　architecture　of　the　check　node　elementary　processor　is　designed.　The　variable　node　update　unit　with　fully　parallel　computation　is　proposed,　which　has　the　advantage　of　low　complexity　and　latency　by　eliminating　forward-backward　operation　and　removing　recursive　computation　among　the　message　vector.　Moreover,　the　FPGA　simulation　over　GF(16)　NB-LDPC　is　given　to　demonstrate　the　efficiency　of　the　presented　design　scheme.　©　2013　Springer-Verlag.