Assembly process simulation of TSV interposer - 文章详情页

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EI Scopus

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TSV　interposer　packaging　is　one　of　the　most　important　applications　for　TSV　technology.　However,　the　warpage　and　residual　stress　arising　from　the　assembly　process　of　TSV　interposer　have　important　influence　on　the　reliability　of　the　package.　In　this　paper,　two　assembly　processes　were　simulated　by　using　the　Finite　Element　Method,　the　evolution　of　the　stresses　and　warpage　during　assembly　were　compared　to　obtain　the　better　process　flow.　According　to　the　chosen　process　flow,　the　reliability　of　micro　bumps　during　assembly　was　discussed,　it　was　confirmed　that　both　the　structure　deformation　(including　deformation　of　chip　and　interposer)　and　TSV-Cu　protrusion　have　effects　on　the　micro　bump　reliability,　it＇s　necessary　to　take　the　relative　orientation　of　the　micro　bumps,　TSVs　and　underfill　fillet　into　consideration　during　packaging　designation.　©　2013　IEEE.

关键词：

Assembly Computer simulation Deformation Electronics packaging Packaging Reliability Three dimensional integrated circuits

作者机构：

[ 1 ] [Chen, Si]College of Mechanical Engineering and Applied Electronics Technology, Beijing University of Technology, Beijing 100124, China
[ 2 ] [Qin, Fei]College of Mechanical Engineering and Applied Electronics Technology, Beijing University of Technology, Beijing 100124, China
[ 3 ] [Xia, Guofeng]College of Mechanical Engineering and Applied Electronics Technology, Beijing University of Technology, Beijing 100124, China
[ 4 ] [Wu, Wei]College of Mechanical Engineering and Applied Electronics Technology, Beijing University of Technology, Beijing 100124, China
[ 5 ] [Yu, Daquan]Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
[ 6 ] [Lu, Yuan]Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

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