A high performance configurable random divider with FGPA and ASIC implementation - 文章详情页

作者：

Hou, Ligang (Hou, Ligang.) | Zhang, Tianran (Zhang, Tianran.) | Wang, Jinhui (Wang, Jinhui.)

收录：

EI Scopus

摘要：

The　divider　is　the　one　of　the　most　important　modules　in　microprocessors.　A　new　algorithm　was　proposed　to　realize　the　decimal　frequency　divider　with　any　number　divide　ratio,　and　the　divide　ratio　was　configurable　by　the　SPI.　In　the　statistical　periods,　the　divide　ratio　is　adjusted　dynamically　by　calculating　the　error　of　clock.　Error　of　divider　can　be　reduced,　and　the　accuracy　after　the　four　rounds　has　come　to　1E-14%　after　4　rounds.　The　implementation　of　decimal　frequency　divider　was　realized　with　FPGA　and　ASIC　(under　180nm　technology).　The　experimental　result　indicated　that　the　decimal　frequency　divider　takes　fewer　resources,　and　its　performance　is　steady　and　reliable　©　2012　IEEE.

关键词：

Application specific integrated circuits Clocks Errors Field programmable gate arrays (FPGA) Frequency dividing circuits

作者机构：

[ 1 ] [Hou, Ligang]VLSI AndSystem Lab, Beijing University of Technology, Beijing, China
[ 2 ] [Zhang, Tianran]VLSI AndSystem Lab, Beijing University of Technology, Beijing, China
[ 3 ] [Wang, Jinhui]VLSI AndSystem Lab, Beijing University of Technology, Beijing, China

通讯作者信息：

电子邮件地址：

houligang@bjut.edu.cn

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