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[会议论文]

A high-accuracy design of frequency divider with FPGA and ASIC implementation

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Author:

Hou, Ligang (Hou, Ligang.) | Zhang, Tianran (Zhang, Tianran.) | Wang, Jinhui (Wang, Jinhui.) | Unfold

Indexed by:

EI Scopus

Abstract:

This paper proposes a new algorithm to realize the decimal frequency divider with any number divide ratio. In the statistical periods, the divide ratio is adjusted dynamically by calculating the error of clock. Error of divider can be reduced, and the accuracy has come to 2.3E-11% after 4 rounds. The implementation of decimal frequency divider was realized with FPGA and ASIC. The article analyzed the resource and performance and compared the result of 180nm and 90nm technology on the ASIC. The layout of the circuit was realized on 180nm technology. The experimental result indicated that the decimal frequency divider takes fewer resources, and its performance is steady and reliable. © 2012 IEEE.

Keyword:

Application specific integrated circuits Integrated circuit design Clocks Field programmable gate arrays (FPGA) Errors Frequency dividing circuits

Author Community:

  • [ 1 ] [Hou, Ligang]VLSI and System Lab., Beijing University of Technology, Beijing, 100124, China
  • [ 2 ] [Zhang, Tianran]VLSI and System Lab., Beijing University of Technology, Beijing, 100124, China
  • [ 3 ] [Wang, Jinhui]VLSI and System Lab., Beijing University of Technology, Beijing, 100124, China
  • [ 4 ] [Li, Yanqing]VLSI and System Lab., Beijing University of Technology, Beijing, 100124, China

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Source :

Year: 2012

Page: 1653-1656

Language: English

Cited Count:

WoS CC Cited Count: 0

SCOPUS Cited Count: 1

30 Days PV: 4

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