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作者:

Hou, Ligang (Hou, Ligang.) | Zhang, Tianran (Zhang, Tianran.) | Wang, Jinhui (Wang, Jinhui.) | Li, Yanqing (Li, Yanqing.)

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EI Scopus

摘要:

This paper proposes a new algorithm to realize the decimal frequency divider with any number divide ratio. In the statistical periods, the divide ratio is adjusted dynamically by calculating the error of clock. Error of divider can be reduced, and the accuracy has come to 2.3E-11% after 4 rounds. The implementation of decimal frequency divider was realized with FPGA and ASIC. The article analyzed the resource and performance and compared the result of 180nm and 90nm technology on the ASIC. The layout of the circuit was realized on 180nm technology. The experimental result indicated that the decimal frequency divider takes fewer resources, and its performance is steady and reliable. © 2012 IEEE.

关键词:

Application specific integrated circuits Clocks Errors Field programmable gate arrays (FPGA) Frequency dividing circuits Integrated circuit design

作者机构:

  • [ 1 ] [Hou, Ligang]VLSI and System Lab., Beijing University of Technology, Beijing, 100124, China
  • [ 2 ] [Zhang, Tianran]VLSI and System Lab., Beijing University of Technology, Beijing, 100124, China
  • [ 3 ] [Wang, Jinhui]VLSI and System Lab., Beijing University of Technology, Beijing, 100124, China
  • [ 4 ] [Li, Yanqing]VLSI and System Lab., Beijing University of Technology, Beijing, 100124, China

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来源 :

年份: 2012

页码: 1653-1656

语种: 英文

被引次数:

WoS核心集被引频次: 0

SCOPUS被引频次: 1

ESI高被引论文在榜: 0 展开所有

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