A 1.1-V 12-bit 20-MS/s pipelined ADC with 1.8-Vpp full-swing in 0.13-μm CMOS - 文章详情页

作者：

Wan, Peiyuan (Wan, Peiyuan.) | Lang, Wei (Lang, Wei.) | Jin, Rui (Jin, Rui.) | Zhang, Chi (Zhang, Chi.) (学者：张弛) | Lin, Pingfen (Lin, Pingfen.)

收录：

EI Scopus

摘要：

A　front-end　unity-gain　1-bit　flip-around　DAC　(FADAC)　is　exploited　in　a　12-bit　opamp-sharing　pipelined　ADC,　allowing　a　1.8-Vpp　full-swing　input　at　a　1.1-V　supply.　The　high　input　swing,　coupled　with　a　large　feedback　factor　(≈1)　of　the　FADAC,　enables　a　low-voltage　low-power　design　for　a　high　resolution　pipelined　ADC.　The　prototype　12-bit　ADC　operating　at　20-MS/s　and　1.1-V　supply　achieves　a　66.4　dB　SNDR　and　76.7　dB　SFDR　with　a　3　MHz　input.　The　ADC　consumes　5.2　mW　of　power　and　occupies　an　active　area　of　0.44　mm2　in　0.13-μm　CMOS.　©　2012　IEEE.

关键词：

Electric power supplies to apparatus Radio waves Analog to digital conversion Operational amplifiers Digital to analog conversion CMOS integrated circuits Pipelines

作者机构：

[ 1 ] [Wan, Peiyuan]Beijing Embedded System Key Lab, Beijing University of Technology, Beijing, 100124, China
[ 2 ] [Lang, Wei]Beijing Embedded System Key Lab, Beijing University of Technology, Beijing, 100124, China
[ 3 ] [Jin, Rui]Beijing Embedded System Key Lab, Beijing University of Technology, Beijing, 100124, China
[ 4 ] [Zhang, Chi]Beijing Embedded System Key Lab, Beijing University of Technology, Beijing, 100124, China
[ 5 ] [Lin, Pingfen]Beijing Embedded System Key Lab, Beijing University of Technology, Beijing, 100124, China

通讯作者信息：

电子邮件地址：

wanpy@bjut.edu.cn

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