Through　Silicon　Via　(TSV)　has　emerged　as　a　good　solution　to　provide　high　density　interconnections　in　three-dimensional　packaging　interconnect　technologies.　However,　the　thermal-mechanical　reliability　is　a　big　issue.　When　the　TSV　is　subjected　to　thermal　load,　large　stress　and　strain　would　be　created　at　the　interface　of　the　materials　because　of　the　great　mismatch　of　CTE.　In　this　paper,　an　axi-symmetric　single　TSV　model　with　RDL　layer　is　taken　into　consideration.　A　static　temperature　difference　of　Δt=165°C　is　carried　out　to　simulate　the　thermal　stress,　effects　of　via　size　and　the　interposer　height　on　the　stress　are　investigated.　Effect　of　SiO2　layer　on　Cu　and　Si　is　also　analyzed.　In　addition,　the　shear　stress　of　interface,　under　thermal　cycles　from　-40°C　to　125　°C,　is　computed.　In　the　simulation　model,　the　kinematic　hardening　material　model　of　Cu　is　used.　©　2012　IEEE.