Effects of via pitch on silicon stress in TSV interposer - 文章详情页

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Through　silicon　vias　(TSVs)　have　been　extensively　studied　because　it　is　a　key　enabling　technology　for　achieving　three　dimensional　(3D)　chip　stacking　and　silicon　interposer　interconnection.　The　large　mismatch　between　the　coefficients　of　thermal　expansion　(CTE)　of　copper　and　silicon　induces　stress　which　is　critical　for　the　TSV　reliability　performance.　This　paper　proposes　analytical　solutions　of　stress　in　a　single　TSV　subjected　to　thermal　loading.　Then　the　thermal　stress　interaction　between　the　vias　induced　on　silicon　has　been　investigated　using　finite　element　modeling.　It　indicates　that　the　interaction　of　thermal　stress　between　vias　becomes　insignificant　as　long　as　the　ratio　of　pitch　to　diameter　of　TSVs　reaches　three.　©　2012　IEEE.

关键词：

Three dimensional integrated circuits Thermal stress Electronics packaging Stress analysis Silicon Thermal expansion

作者机构：

[ 1 ] [An, Tong]College of Mechanical Engineering and Applied Electronics Technology, Beijing University of Technology, Beijing, 100124, China
[ 2 ] [Qin, Fei]College of Mechanical Engineering and Applied Electronics Technology, Beijing University of Technology, Beijing, 100124, China
[ 3 ] [Wu, Wei]College of Mechanical Engineering and Applied Electronics Technology, Beijing University of Technology, Beijing, 100124, China
[ 4 ] [Yu, Daquan]Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
[ 5 ] [Wan, Lixi]Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
[ 6 ] [Wang, Jun]Materials Science Department, Fudan University, Shanghai 200433, China

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