With　the　rapid　development　of　deep　submicron　(DSM)　VLSI　circuit　design,　many　issues　such　as　time　closure　and　power　consumption　are　making　the　physical　design　more　and　more　challenging.　This　paper　proposes　a　method　aiding　in　low　clock　skew　which　is　applicable　to　the　clock　tree　synthesis　(CTS)　design　flow.　The　method　works　by　breaking　up　the　original　clock　root　into　several　pseudo　clock　sources　at　the　gate　level.　The　method　has　been　used　in　the　physical　design　of　YAK　SoC　chip　and　achieves　good　results.　©　2011　IEEE.