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Abstract：
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate. In this paper, we give the different initial step for different modulation and present a hardware implementation of the extended min-sum (EMS) decoding algorithm for non-binary LDPC codes. Moreover, an FPGA simulation over GF(16) is given to demonstrate the efficiency of the presented techniques. © 2011 IEEE.
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Year： 2011
Language： English
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WoS CC Cited Count： 0
SCOPUS Cited Count： 2
ESI Highly Cited Papers on the List： 0 Unfold All
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30 Days PV： 2
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