A 1.2-V 250-MS/s 8-bit pipelined ADC in 0.13-μm CMOS - 文章详情页

作者：

Wan, Peiyuan (Wan, Peiyuan.) | Lang, Wei (Lang, Wei.) | Fang, Di (Fang, Di.) | Cui, Wei (Cui, Wei.) | Lin, Pingfen (Lin, Pingfen.)

收录：

EI Scopus

摘要：

This　paper　describes　the　implementation　and　experimental　results　of　a　250　MS/s　8-bit　pipelined　analog-to-digital　converter　(ADC)　in　a　0.13-μm　CMOS　process.　The　ADC　uses　a　dedicated　sample-and-hold　amplifier　(SHA)　to　achieve　excellent　linearity　performances　with　high　SFDR　and　very　flat　SNDR.　Stage　scaling　in　the　pipeline　chain　is　adopted　to　lower　the　power　consumption.　The　ADC　measures　a　SFDR　of　over　60　dB　and　7.45　ENOB　at　250　Ms/s　with　an　input　frequency　of　19　MHz.　SNDR　only　drops　1.7dB　with　input　frequency　increasing　from　dc　to　over　70MHz.　Including　all　analog　and　digital　blocks,　the　total　power　dissipation　of　the　ADC　is　60mW　from　a　1.2V　power　supply.　The　active　area　is　800　μmx700　μm.　©　2011　IEEE.

关键词：

Analog integrated circuits Analog to digital conversion CMOS integrated circuits Digital to analog conversion Operational amplifiers Pipelines

作者机构：

[ 1 ] [Wan, Peiyuan]Beijing Embedded System Key Lab., Beijing University of Technology, Beijing, China
[ 2 ] [Lang, Wei]Beijing Embedded System Key Lab., Beijing University of Technology, Beijing, China
[ 3 ] [Fang, Di]Beijing Embedded System Key Lab., Beijing University of Technology, Beijing, China
[ 4 ] [Cui, Wei]Beijing Embedded System Key Lab., Beijing University of Technology, Beijing, China
[ 5 ] [Lin, Pingfen]Beijing Embedded System Key Lab., Beijing University of Technology, Beijing, China

通讯作者信息：

电子邮件地址：

wanpy@bjut.edu.cn

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