Recently　there　has　been　a　growing　interest　in　models　and　methods　targeted　towards　the　design　of　video　stream　parallel　processing,　and　the　applications　tend　to　be　highly　bursty　and　dependent　parallel.　As　a　result,　the　most　existing　models　are　not　suitable　for　dealing　with　such　system　design.　In　this　paper,　we　present　an　Event　Count　Model　(ECM)　to　capturing　the　timing　properties　of　video　stream　processing　in　the　hierarchical　system　structure;　and　we　also　use　Continuous　Markov　Chain　modeling　and　high　level　colored　time　Petri　net　to　describe　the　multiprocessor　system　architecture　and　co-design　of　software　and　hardware.　Simulations　of　the　asynchronous　and　concurrent　interactions　of　system,　and　formal　co-verification　approach　with　CPN　Tools　is　proposed　and　a　case　of　h.264　encoder　on　MPSoC　is　used　for　illustrate　these　explanations.　©　2011　IEEE.