A network on chip architecture and performance evaluation - 文章详情页

作者：

Zhang, Wang (Zhang, Wang.) | Hou, Ligang (Hou, Ligang.) | Zuo, Lei (Zuo, Lei.) | Peng, Zhenyu (Peng, Zhenyu.) | Wu, Wuchen (Wu, Wuchen.) (学者：吴武臣)

收录：

EI Scopus

摘要：

Networks-on-chip　(NoCs)　have　emerged　as　an　alternative　to　ad-hoc　wiring　or　bus-based　global　interconnection　in　Systems-on-Chip　(SoCs).　The　architecture　of　network　significantly　determines　system　performance.　This　paper　proposes　a　network　on　chip　architecture　with　2-demention　mesh　topology,　odd-even　routing　algorithm,　wormhole　switching　technique　and　only　input　buffers.　The　size　of　packet　is　20　bytes　and　that　of　flit　is　5　bytes.　The　performance　of　proposed　architecture　is　evaluated　based　on　metrics　of　latency　and　throughput　per　channel　under　Constant　Bit　Rate　(CBR)　and　Bursty　traffic.　For　the　proposed　architecture,　the　evaluation　results　reveal　that　the　average　latency　of　whole　network　channels　is　1.97　cycles　under　CBR　traffic　and　1.92　cycles　under　Bursty　traffic.　The　average　throughput　of　whole　network　channels　is　8.8555　Gbps　under　CBR　traffic　and　8.8212　Gbps　under　Bursty　traffic.　©　2010　IEEE.

关键词：

Architecture Computer architecture Mesh generation MESH networking Network architecture Network-on-chip Network routing Servers Topology Trusted computing

作者机构：

[ 1 ] [Zhang, Wang]VLSI and System Lab., Beijing University of Technology, Beijing, China
[ 2 ] [Hou, Ligang]VLSI and System Lab., Beijing University of Technology, Beijing, China
[ 3 ] [Zuo, Lei]VLSI and System Lab., Beijing University of Technology, Beijing, China
[ 4 ] [Peng, Zhenyu]VLSI and System Lab., Beijing University of Technology, Beijing, China
[ 5 ] [Wu, Wuchen]VLSI and System Lab., Beijing University of Technology, Beijing, China

通讯作者信息：

电子邮件地址：

zhangwang@emails.bjut.edu.cn

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