A　digital　decimation　filter　used　in　Δ　-　Σ　ADC　is　designed　and　introduced　in　this　paper.　The　designed　filter　has　a　multi-stage　structure　which　is　comprised　of　a　stage　CIC　filter,　two　stage　half-band　filters,　and　a　stage　compensation　filter.　The　CSD　coding,　＇Hognenauer　cut-off　theory＇,　frequency　response　masking　approach　and　some　other　techniques　are　used　to　improve　the　performance　of　the　chip　and　reduce　the　chip　area　and　power　consumption.　This　down-sampling　filter　is　achieved　by　algorithm　modeling　using　MATLAB　and　hardware　implementation　using　Verilog　HDL.　The　performance　indicators　raised　are　achieved.　©　2010　IEEE.