A 22mW 10-bit 150-MS/s pipelined ADC in 1.2V 65nm CMOS - 文章详情页

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This　paper　presents　the　low-power　implementation　of　a　10-bit　150-MS/s　pipelined　analog-to-digital　converter　(ADC)　in　a　standard　65　nm　digital　CMOS.　The　ADC　removes　the　track-and-hold　amplifier　(THA)　to　reduce　the　power　consumption.　A　1.5　bit/stage　architecture　is　used　in　the　first　stage　to　lower　front-end　design　complexity.　Three　2.5-bit　stages　are　followed　to　reduce　the　stage　number　in　the　pipeline　chain.　Operational　amplifiers　(op-amps)　sharing　technique　is　used　between　consecutive　stages　for　further　power　saving.　A　high　swing　continuous-time　common　mode　feedback　(CMFB)　circuit　is　adopted　in　the　op-amp　design.　Simulation　results　shows　the　proposed　ADC　achieves　9.8　ENOB　with　a　23　MHz　input.　The　power　consumption　is　22　mW　from　a　1.2　V　supply　voltage.　The　active　area　is　640　μm　×　470　μm.　©2010　IEEE.

关键词：

Analog to digital conversion CMOS integrated circuits Continuous time systems Electric power utilization Integrated circuit design Operational amplifiers Pipelines

作者机构：

[ 1 ] [Wang, Jiacheng]Beijing Embedded System Key Lab., Beijing University of Technology, Beijing 100124, China
[ 2 ] [Zhu, Di]Beijing Embedded System Key Lab., Beijing University of Technology, Beijing 100124, China
[ 3 ] [Guo, Lele]Beijing Embedded System Key Lab., Beijing University of Technology, Beijing 100124, China
[ 4 ] [Jin, Rui]Beijing Embedded System Key Lab., Beijing University of Technology, Beijing 100124, China
[ 5 ] [Wan, Peiyuan]Beijing Embedded System Key Lab., Beijing University of Technology, Beijing 100124, China
[ 6 ] [Lin, Pingfen]Beijing Embedded System Key Lab., Beijing University of Technology, Beijing 100124, China

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