MBIST design and implementation of a H.264/AVC video decoder chip - Details

Author：

Hou, Ligang (Hou, Ligang.) | Wu, Wuchen (Wu, Wuchen.) (Scholars：吴武臣) | Zhu, Jiahui (Zhu, Jiahui.)

Indexed by：

EI Scopus

Abstract：

This　paper　implemented　MBIST　in　a　H.264/AVC　video　decoder　chip,　Neptune.　Neptune　has　1.5　million　gates,　37　memory　blocks.　In　need　of　testing,　a　complete　design　for　test　should　be　done.　This　paper　mainly　designed　and　implemented　Memory　BIST　targeting　the　34　RAM　block,　except　the　3　ROM　blocks.　The　design　included　building　design　flow,　choosing　algorithm,　generating　background　data　and　BIST　controller　integration.　By　BIST　controller　reuse,　circuit　area　was　saved.　Working　mode　simulation,　test　time　analysis,　fault　coverage　analysis,　circuit　performance　evaluation　were　done.　The　result　showed　that　the　MBIST　achieved　100%　fault　coverage　by　a　2.49%　increase　in　chip　area.　©　2010　IEEE.

Keyword：

Signal processing Decoding Built-in self test Architectural design Motion Picture Experts Group standards Random access storage

Author Community：

[ 1 ] [Hou, Ligang]VLSI and System Lab., Beijing University of Technology, Beijing, China
[ 2 ] [Wu, Wuchen]VLSI and System Lab., Beijing University of Technology, Beijing, China
[ 3 ] [Zhu, Jiahui]HSC-DAC Dept., Analog Devices Inc., Beijing Design Center, Beijing, China