Hardware design of image information processor based on ADSP-TS201 DSPs - 文章详情页

作者：

Qiang, Wu (Qiang, Wu.) | Qing, Gao (Qing, Gao.) | Xuwen, Li (Xuwen, Li.) | Kebin, Jia (Kebin, Jia.) (学者：贾克斌)

收录：

EI Scopus

摘要：

This　paper　studies　on　the　hardware　design　and　implementation　of　a　universal　multi-DSP　and　FPGA　image　information　processor　in　accordance　with　the　PCI-E　and　CPCI　specifications.　The　image　information　processor　features　two　clusters　of　total　four　ADSP-TS201　TigerSHARC　DSPs　from　ADI　as　the　kernel　processing　unit,　reconfigurable　framework　implemented　by　two　Xilinx　Virtex-5　FXT　FPGA　chips.　Taking　full　advantage　of　the　high　performance,　unprecedented　I/O　bandwidth　of　TigerSHARC　DSP　and　Virtex-5　FXT　FPGA,　the　processor　can　easily　meet　the　huge　image　processing　and　computing　work.　The　hardware　design　of　high　speed　Linkport　interconnection　between　TS201　DSPs　and　FPGA　chips　is　described.　©　2009　IEEE.

关键词：

Integrated circuit design Field programmable gate arrays (FPGA) Imaging systems Computer peripheral equipment

作者机构：

[ 1 ] [Qiang, Wu]College of Electronic and Control Engineering, Beijing University of Technology, Beijing, China
[ 2 ] [Qing, Gao]College of Electronic and Control Engineering, Beijing University of Technology, Beijing, China
[ 3 ] [Xuwen, Li]College of Life Science and Bio-engineering, Beijing University of Technology, Beijing, China
[ 4 ] [Kebin, Jia]College of Electronic and Control Engineering, Beijing University of Technology, Beijing, China

通讯作者信息：

电子邮件地址：

wuqiang@bjut.edu.cn

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