The　Network-on-Chip　(NoC)　has　been　recognized　as　a　paradigm　to　solve　System-on-Chip　(SoC)　design　challenges,　due　to　many　of　the　problems　that　will　be　faced　by　the　designers　of　multi-billion　transistor　chips.　The　infrastructure　of　network　tail　determines　system　performance　and　cost.　The　virtual　channel　buffer　depth　of　tail＇s　input　channel　is　one　of　the　key　design　problems.　The　deep　input　channel　buffer　depth,　which　is　at　each　tail　in　the　NoC,　increases　the　overall　area　of　chips.　At　the　same　time,　depending　on　the　network　workload,　increasing　the　buffer　size　can　reduce　the　network　latency　by　orders　of　magnitude.　This　paper　analyses　the　buffer　depth　of　2-Dimension　mesh　topology　NoC　with　odd-even　routing　algorithm　based　on　NoC　Interconnect　Routing　and　Application　Modeling　(NIRGAM)　simulator.　The　analysis　results　reveal　that　the　optimized　input　First-In-Fist-Out　(FIFO)　buffer　depth　of　virtual　channel　has　not　relationship　with　network　scale　for　2-Dimension　mesh　topology　NoC　at　Constant　Bit　Rate　(CBR)　traffic　condition.　The　optimized　input　FIFO　buffer　depth　of　virtual　channel　is　all　6　for　2X2,　3X3　and　4X4　mesh　topology　NoC.　©2009　IEEE.