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The specific application of power devices has imposed the requirement for intensive investigation of their reliability. In this paper we have investigated the reliability and failure mechanism of power VDMOS. In constant-stress accelerated life test, the three different temperatures (150C, 165C and 180C) are imposed on the devices. Under the bias VDS=7.5V, IDS=0.8A, and the channel temperature T=117C, the average lifetime is 3.67106 h, the activation energy E is 0.54eV, and the main failuremechanism is gate damage. ©2009 IEEE.
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