A　low　voltage　low　power　sigma　delta　modulator　was　presented.　A　sigma　delta　modulator　architecture　which　was　very　adapt　to　low　voltage　low　power　applications　was　proposed.　With　the　advantage　of　both　unity　gain　sigma　delta　modulator　and　traditional　sigma　delta　modulator,　it　relaxed　the　requirement　of　the　OTA　performance　and　decreased　the　complex　of　the　circuit.　For　lower　power　consumption　as　soon　as　possible,　the　technique　of　negative　resistance　load　was　used　to　improve　the　dc　gain　of　the　current　mirror　OTA　and　the　technique　of　Class-AB　output　stage　was　used　for　lower　power　consumption.　Simulation　results　showed　that　with　0.18um　CMOS　technology,　20　KHz　signal　bandwidth　and　oversampling　rate　of　156,　the　modulator　achieved　93dB　dynamic　range,　the　power　consumption　was　500uW　under　1V　supply　voltage　and　the　chip　core　size　was　0.5mm2.　Measure　results　showed　that　with　2MHz　sampling　frequency　and　1KHz　input　signal　the　sigma　delta　modulator　achieved　65dB　SNR　and　60dB　SNDR.　©2009　IEEE.