Implementation of high-speed high-resolution data conversion system using FPGA - 文章详情页

作者：

Cao, Xiaoqiu (Cao, Xiaoqiu.) | Zeng, Jin (Zeng, Jin.) | Yang, Tao (Yang, Tao.)

收录：

EI Scopus

摘要：

This　paper　analyzes　the　implementation　of　high-speed　high-resolution　data　conversion　system　based　on　Subranging　A/D　model　in　detail.　We　use　a　10　bit　ADC　and　an　8　bit　ADC　to　construct　the　Subranging　A/D　system　and　then　make　a　simulation　by　QuartusII.　The　result　of　the　experiment　shows　that　the　system＇s　sampling　rates　is　17MHz,　and　the　resolution　is　16　bit,　so　it　can　solve　an　antinomy　between　sampling　rates　and　resolution　,　which　is　prevalent　in　current　market.　©　2007　IEEE.

关键词：

Data handling Analog to digital conversion Field programmable gate arrays (FPGA)

作者机构：

[ 1 ] [Cao, Xiaoqiu]College of Electronic and Control Engineering, Beijing University of Technology, Beijing 100022, China
[ 2 ] [Zeng, Jin]College of Electronic and Control Engineering, Beijing University of Technology, Beijing 100022, China
[ 3 ] [Yang, Tao]College of Electronic and Control Engineering, Beijing University of Technology, Beijing 100022, China

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