Solder　joints　serve　as　mechanical,　thermal　and　electrical　interconnections　between　the　electronic　packages　and　the　printed　circuit　board　(PCB).　Fracture　of　the　solder　joint　is　the　most　common　failure　mechanism　in　microsystem　packages　due　to　mechanical　loads.　In　order　to　satisfy　the　demand　for　understanding　the　process　of　solder　joint　fracture,　there　is　a　need　for　a　validated　model,　which　is　simple,　reliable,　and　able　to　clarify　of　physics-of-failure　of　solder　joint　for　design　improvement.　In　this　paper,　the　lattice　model　has　been　established　to　simulate　the　process　of　solder　joint　fracturing.　The　results　show　that　the　proposed　lattice　model　can　easily　be　used　to　predict　the　cracking　of　solder　joint　under　tensile　loading.　The　predicted　crack　pattern　agrees　well　with　that　observed　in　experiments.　©2007　IEEE.