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作者:

Zhang, Nai-Ran (Zhang, Nai-Ran.) | Li, Mo (Li, Mo.) | Wu, Chen (Wu, Chen.)

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EI Scopus

摘要:

This paper proposes advanced motion compensation VLSI architecture for H.264/AVC decoder system. In the paper, passive reuse and active reuse utilize memory bandwidth efficiently with 50% optimization compared with traditional design. Highly parallel cross filter style makes sub-pixel interpolation high throughput and low latency. Experiment and simulation results show that the architecture supports 30fps digital-HDTV (1280×720) clocking at 60MHz with 100MHz DRAM controller. Moreover, the architecture is modularized and easy to be integrated. ©2006 IEEE.

关键词:

Bandwidth Computer aided design Dynamic random access storage High definition television Image coding Motion compensation Motion Picture Experts Group standards VLSI circuits

作者机构:

  • [ 1 ] [Zhang, Nai-Ran]VLSI and System Lab, Beijing University of Technology, Beijing 100022, China
  • [ 2 ] [Li, Mo]VLSI and System Lab, Beijing University of Technology, Beijing 100022, China
  • [ 3 ] [Wu, Chen]VLSI and System Lab, Beijing University of Technology, Beijing 100022, China

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来源 :

年份: 2006

页码: 1896-1898

语种: 英文

被引次数:

WoS核心集被引频次: 0

SCOPUS被引频次: 3

ESI高被引论文在榜: 0 展开所有

万方被引频次:

中文被引频次:

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