A　new　method　is　proposed　that　uses　a　combined　approach　of　inputs　state　assignment　and　clock　signal　assignment　for　idle　footed　dual　Vt　dominos　at　two　typical　die　temperatures　in　nanometer　CMOS　technologies.　Simulations　based　on　45nm　BSIM4　models　show　that　the　previously　CHIH　state　(the　clock　signal　and　inputs　are　all　high)　is　only　effective　to　suppress　the　leakage　current　of　footed　dual　Vt　dominos　at　high　temperature　excluding　the　high　fan-in　wide　gates　for　the　gate　leakage　current　produced　by　the　footer　NMOS.　For　the　high　fan-in　footed　dominos　at　high　temperature　and　all　types　footed　dominos　at　room　temperature,　the　CLIH　(the　clock　signal　is　low　and　inputs　are　high)　and　CLIL　(the　clock　signal　and　inputs　are　all　low)　states　are　preferable　to　reduce　the　leakage　current.　Further,　the　influence　of　the　process　parameter　variations　on　the　leakage　current　characteristics　of　the　footed　dual　V　t　dominos　is　also　evaluated.　©　2006　IEEE.