Low power wide dominos design in sub-65nm CMOS technologies - 文章详情页

作者：

Jinhui, Wang (Jinhui, Wang.) | Na, Gong (Na, Gong.) | Ligang, Hou (Ligang, Hou.) | Limin, Dong (Limin, Dong.) | Wuchen, Wu (Wuchen, Wu.) (学者：吴武臣)

收录：

EI Scopus

摘要：

Two　novel　low　power　wide　OR　domino　designs　are　presented　in　this　paper.　With　the　same　delay　time,　the　two　designed　dominos　decrease　the　active　power　by　8.92%　to　17.25%　and　13.79%　to　25.84%　as　compared　to　the　standard　dual　V　t　dominos　in　a　45nm　CMOS　technology.　In　the　meantime,　the　total　leakage　current　is　reduced　significantly　at　two　typical　die　temperatures.　©2006　IEEE.

关键词：

CMOS integrated circuits Computer aided design Electric network analysis Leakage currents Time delay

作者机构：

[ 1 ] [Jinhui, Wang]VLSI and System Lab., Beijing University of Technology, Beijing 100022, China
[ 2 ] [Na, Gong]College of Electronic and Informational Engineering, Hebei University, Baoding 071002, China
[ 3 ] [Ligang, Hou]VLSI and System Lab., Beijing University of Technology, Beijing 100022, China
[ 4 ] [Limin, Dong]VLSI and System Lab., Beijing University of Technology, Beijing 100022, China
[ 5 ] [Wuchen, Wu]VLSI and System Lab., Beijing University of Technology, Beijing 100022, China

通讯作者信息：

电子邮件地址：

wangjinhui888@emails.bjut.edu.cn

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