In　this　paper,　we　proposed　a　parallel　and　pipeline　architecture　for　the　sub-pixel　interpolation　filter　in　H.264/AVC　conformed　HDTV　decoder.　To　efficiently　use　the　bus　bandwidth,　we　bring　forward　two　memory　access　optimization　strategies　to　avoid　redundant　data　transfer　and　improve　data　bus　utilization.　To　improve　the　processing　throughput,　we　use　parallel　and　multi-stage　pipeline　architecture　for　conducting　data　transmission　and　interpolation　filtering　in　parallel.　As　compared　to　the　traditional　designs,　our　scheme　offers　60%　reduced　memory　data　transfer.　While　clocking　at　66MHz,　our　design　can　support　1280x720@30Hz　processing　throughput.　The　proposed　design　is　suitable　for　system-on-chip　design.　©　2005　IEEE.