Dummy TSV based bit-line optimization in 3D on-chip memory - Details

Author：

Xiaowei, C. (Xiaowei, C..) | Pourbakhsh, S.A. (Pourbakhsh, S.A..) | Ligang, H. (Ligang, H..) | Na, G. (Na, G..) | Jinhui, W. (Jinhui, W..)

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Abstract：

In　Three-dimensional　(3D)　Integrated　Circuit　(IC),　dummy　TSVs　are　often　required　for　thermal　and　thinning　concerns.　In　this　paper,　we　propose　to　use　those　＇timing　wasteful＇　dummy　TSVs　for　timing　optimization　in　on-chip　memory,　that　is　to　replace　bit　line　delay　cells　with　dummy　TSVs.　The　delay　time　is　measured　with　different　TSV　sizes,　TSV　arrays,　and　technology　nodes.　Three　memories　are　employed　to　verify　the　feasibility　and　reliability　of　the　proposed　technology.　©　2016　IEEE.

Keyword：

3D IC; bit line; delay cell; TSV

Author Community：

[ 1 ] [Xiaowei, C.]Department of Electrical and Computer Engineering, North Dakota State University, Fargo, ND 58102, United States
[ 2 ] [Pourbakhsh, S.A.]Department of Electrical and Computer Engineering, North Dakota State University, Fargo, ND 58102, United States
[ 3 ] [Ligang, H.]Department of Electrical and Computer Engineering, North Dakota State University, Fargo, ND 58102, United States
[ 4 ] [Na, G.]VLSI and System Lab, Beijing University of Technology, Beijing, 100124, China
[ 5 ] [Jinhui, W.]Department of Electrical and Computer Engineering, North Dakota State University, Fargo, ND 58102, United States

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Source ：

IEEE International Conference on Electro Information Technology

ISSN： 2154-0357

Year： 2016

Volume： 2016-August

Page： 580-585

Language： English

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SCOPUS Cited Count： 2

ESI Highly Cited Papers on the List： 0 Unfold All

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30 Days PV： 1

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信息学部

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