A TSV alignment design for multilayer 3D IC - 文章详情页

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Through-silicon　via　(TSV)　achieves　interconnects　of　multiple　dies　in　a　3D　IC.　Previous　researches　show　that　irregular　TSV　placement　may　cause　reliability　issues　in　manufacturing.　Therefore,　this　paper　forwards　a　TSV　alignment　design　in　acquiring　an　overlap-free　near-regular　TSV　placement.　This　design　features　a　TSV　alignment　algorithm　which　aligns　an　irregular　TSV　placement　into　a　near-regular　one.　Experiments　are　conducted　on　2D-3D　transformation　of　IBM　benchmark　circuits.　Results　show　that　this　design　successfully　realizes　a　near-regular　overlap-free　TSV　placement.　©　2015　IEEE.

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[ 1 ] [Zhao, W.]VLSI and System Lab, Beijing University of Technology, Beijing, 100124, China
[ 2 ] [Hou, L.]VLSI and System Lab, Beijing University of Technology, Beijing, 100124, China
[ 3 ] [Peng, X.]VLSI and System Lab, Beijing University of Technology, Beijing, 100124, China
[ 4 ] [Wang, J.]VLSI and System Lab, Beijing University of Technology, Beijing, 100124, China
[ 5 ] [Fu, J.]VLSI and System Lab, Beijing University of Technology, Beijing, 100124, China
[ 6 ] [Yang, Y.]VLSI and System Lab, Beijing University of Technology, Beijing, 100124, China

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