Design and testing of CMOS compatible EEPROM - 文章详情页

作者：

Yin, H. (Yin, H..) | Peng, X. (Peng, X..) | Wan, P. (Wan, P..) | Wang, J. (Wang, J..) | Hou, L. (Hou, L..)

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Scopus

摘要：

A　single-poly　CMOS　compatible　Electrically　Erasable　Programmable　Read-Only　Memory　(EEPROM)　is　presented　in　this　paper.　The　difference　between　the　traditional　structure　and　the　proposed　structure　is　that　the　capacitance　between　control　gate　and　floating　gate,　and　the　capacitance　between　floating　gate　and　channel　are　fabricated　on　the　same　layer.　This　approach　makes　EEPROM　and　periphery　circuits　can　be　fabricated　in　the　standard　CMOS　technology,　so　development　cost　is　greatly　reduced.　An　8　byte　×　8　bits　EEPROM　array　including　readout　circuit　and　charge　pump　circuit　is　implemented　in　TSMC　0.35μm　CMOS　technology　in　this　paper.　Meanwhile,　pre-charge　scheme　is　used　in　the　readout　circuit.　©　2015　IEEE.

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作者机构：

[ 1 ] [Yin, H.]VLSI and System Lab, Beijing University of Technology, Beijing, 100124, China
[ 2 ] [Peng, X.]VLSI and System Lab, Beijing University of Technology, Beijing, 100124, China
[ 3 ] [Wan, P.]Beijing Embedded System Key Lab, Beijing University of Technology, Beijing, 100124, China
[ 4 ] [Wang, J.]VLSI and System Lab, Beijing University of Technology, Beijing, 100124, China
[ 5 ] [Wang, J.]Department of Electrical and Computer Engineering, North Dakota State University, Fargo, ND 58102, United States
[ 6 ] [Hou, L.]VLSI and System Lab, Beijing University of Technology, Beijing, 100124, China

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