Through-silicon　vias　(TSV)　are　facing　unexpected　thermo-mechanical　reliability　problems　due　to　the　coefficient　of　thermal　expansion　(CTE)　mismatch　between　various　materials　in　TSVs.　During　applications,　thermal　stresses　induced　by　CTE　mismatch　will　have　a　negative　impact　on　other　devices　connecting　with　TSVs,　even　leading　to　failure.　Therefore,　it　is　essential　to　investigate　the　stress　distribution　evolution　in　the　TSV　structure　under　thermal　loads.　In　this　report,　TSVs　were　heated　to　450A　degrees　C　at　different　heating　rates,　then　cooled　down　to　room　temperature　after　a　30-min　dwelling.　After　heating　treatment,　TSV　samples　exhibited　different　Cu　deformation　behaviors,　including　Cu　intrusion　and　protrusion.　Based　on　the　different　Cu　deformation　behaviors,　stress　in　Si　around　Cu　vias　of　these　samples　was　measured　and　analyzed.　Results　analyzed　by　Raman　spectrums　showed　that　the　stress　distribution　changes　were　associated　with　Cu　deformation　behaviors.　In　the　area　near　the　Cu　via,　Cu　protrusion　behavior　might　aggravate　the　stress　in　Si　obtained　from　the　Raman　measurement,　while　Cu　intrusion　might　alleviate　the　stress.　The　possible　reason　was　that　in　this　area,　the　compressive　stress　induced　by　thermal　loads　might　be　the　dominant　stress.　In　the　area　far　from　the　Cu　via,　thermal　loads　tended　to　result　in　a　tensile　stress　state　in　Si.