The design and optimization for deep submicron SOC power mesh - 文章详情页

作者：

Wang, C. (Wang, C..) | Zhang, W. (Zhang, W..) | Lin, P. (Lin, P..) | Wan, P. (Wan, P..) | Zhu, X. (Zhu, X..)

收录：

Scopus PKU CSCD

摘要：

To　reduce　the　amount　of　redundancy　caused　by　the　traditional　design　of　power　mesh　for　SOC,　a　non-uniform　ladder　type　power　mesh　was　proposed　in　this　paper　by　limiting　module　place　to　make　sure　of　the　optimized　area　and　optimizing　line　width　to　release　the　routing　space.　This　method　could　not　only　effectively　reduce　the　chip　area　and　total　length　of　signal　line,　but　also　optimize　the　power　consumption.　Based　on　SMIC　0.18　Eflash　1P4M　process,　the　chip＇s　circuit　and　layout　were　designed　using　Synopsys　IC　Compiler.　After　the　tape-out　and　the　test,　the　results　show　that　the　chip　area　reduces　by　8.69%　and　power　consumption　reduces　by　4.04%.　This　optimized　method　has　some　reference　for　the　power　mesh　design.　©,　2015,　NUAA　Printing　House.　All　right　reserved.

关键词：

Area optimization; Physical design; Power mesh; Power optimization

作者机构：

[ 1 ] [Wang, C.]College of Electronic Information & Control Engineering, Beijing University of Technology, Beijing, 100124, China
[ 2 ] [Zhang, W.]College of Electronic Information & Control Engineering, Beijing University of Technology, Beijing, 100124, China
[ 3 ] [Lin, P.]College of Electronic Information & Control Engineering, Beijing University of Technology, Beijing, 100124, China
[ 4 ] [Wan, P.]College of Electronic Information & Control Engineering, Beijing University of Technology, Beijing, 100124, China
[ 5 ] [Zhu, X.]College of Electronic Information & Control Engineering, Beijing University of Technology, Beijing, 100124, China

通讯作者信息：

[Wang, C.]College of Electronic Information & Control Engineering, Beijing University of TechnologyChina

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