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学者姓名：代岩伟
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摘要 ：
The mismatch effect in weldment is widely to be found in engineering practices. In this paper, the material mismatch effect on the mode II creep crack tip field is investigated and discussed. The mismatch effect on the C (t)-integral is presented. Both the local mismatch and the general mismatch are found to play important role in C (t)-integral under mode II condition. The mismatch effect on the stress field of mode II creep crack is also studied. The two-order term solutions are adopted to characterize the material mismatch effect on the mode II creep crack. The effect of creep coefficient, creep exponent as well as the HAZ thickness on the high order term solutions are also presented. Some typical cases by considering general mismatch and local mismatch effect are given to make a comparisons between the HRR field, FE solutions and the two-order term solutions. It can be seen that the two-order term solutions can coincide with the full field FE solutions quite reasonably regardless of creep extent, creep exponent, mismatch factor, and HAZ thickness. The material mismatch effect on the high order term solutions is significant under some conditions. A theoretical formula is presented to show the implication of material mismatch effect on creep crack growth under mode II condition based on stress damage model.
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| GB/T 7714 | Dai, Yanwei , Qin, Fei , Liu, Yinghua et al. Characteristics and implications of material mismatch on mode II creep crack tip field: Theoretical analysis and numerical investigation [J]. | THEORETICAL AND APPLIED FRACTURE MECHANICS , 2021 , 114 . |
| MLA | Dai, Yanwei et al. "Characteristics and implications of material mismatch on mode II creep crack tip field: Theoretical analysis and numerical investigation" . | THEORETICAL AND APPLIED FRACTURE MECHANICS 114 (2021) . |
| APA | Dai, Yanwei , Qin, Fei , Liu, Yinghua , Chen, Haofeng , Berto, Filippo . Characteristics and implications of material mismatch on mode II creep crack tip field: Theoretical analysis and numerical investigation . | THEORETICAL AND APPLIED FRACTURE MECHANICS , 2021 , 114 . |
| 导入链接 | NoteExpress RIS BibTex |
摘要 ：
Through silicon via (TSV) is a crucial interconnection structure in 3-D integrated circuits. However, protrusion and intrusion of TSV-Cu caused by annealing could lead to cracking and failure of back-end-of-line (BEOL) layers and TSV interconnects due to mismatch of coefficient of thermal expansion. In this paper, optimizations of TSV interconnects and BEOL layers under annealing process are investigated based on fracture evaluation. Influences of geometrical factors including the TSV geometry dimension, the distance between TSV and BEOL layers, and pitch size of Cu via on energy release rate and J-integral are studied for TSV interconnects and BEOL layers with cracks. Effect of material properties for low k dielectrics on interfacial fracture of BEOL layers and TSV interconnects is also given. Optimized geometrical factors and optimized material properties of low k dielectrics are presented in this paper. Fracture-based method sheds a light on emerging electronic packaging optimization.
关键词 ：
annealing process annealing process J-integral J-integral TSV interconnect TSV interconnect energy release rate energy release rate BEOL layer BEOL layer
引用：
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| GB/T 7714 | Qin, F. , Zhang, M. , Dai, Y. et al. Optimization of TSV interconnects and BEOL layers under annealing process through fracture evaluation [J]. | FATIGUE & FRACTURE OF ENGINEERING MATERIALS & STRUCTURES , 2020 , 43 (7) : 1433-1445 . |
| MLA | Qin, F. et al. "Optimization of TSV interconnects and BEOL layers under annealing process through fracture evaluation" . | FATIGUE & FRACTURE OF ENGINEERING MATERIALS & STRUCTURES 43 . 7 (2020) : 1433-1445 . |
| APA | Qin, F. , Zhang, M. , Dai, Y. , Chen, P. , An, T. , He, H. et al. Optimization of TSV interconnects and BEOL layers under annealing process through fracture evaluation . | FATIGUE & FRACTURE OF ENGINEERING MATERIALS & STRUCTURES , 2020 , 43 (7) , 1433-1445 . |
| 导入链接 | NoteExpress RIS BibTex |
摘要 ：
Sintered silver is a very promising die-attach material which is hopeful to be adopted in the third generation of power electronics. Thermal conductivity is an important index to characterize the heat conduction capacity of sintered silver. In this paper, a numerical model to compute equivalent thermal conductivity of sintered silver is proposed and verified based on the method with microstructure characteristics modelling. Based on the computations, the variations of the equivalent thermal conductivity for sintered silver are presented where porosity effect and aging effect are taken into account. Comparisons of heat flux distributions and temperature distributions of sintered silver with different porosity ratios and aging time are also made. A theoretical model is proposed to evaluate the equivalent thermal conductivity of sintered silver, which agrees quite reasonably with existed experimental results. Based on the proposed model, a theoretical model to predict the equivalent thermal conductivity of sintered silver considering aging effect is also presented. The method given in this paper can be used to predict the equivalent thermal conductivity of sintered silver under different loading conditions considering aging effect.
关键词 ：
Numerical simulation Numerical simulation Sintered silver Sintered silver Equivalent thermal conductivity Equivalent thermal conductivity Porosity Porosity Microstructure Microstructure
引用：
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| GB/T 7714 | Qin, Fei , Hu, Yuankun , Dai, Yanwei et al. Evaluation of thermal conductivity for sintered silver considering aging effect with microstructure based model [J]. | MICROELECTRONICS RELIABILITY , 2020 , 108 . |
| MLA | Qin, Fei et al. "Evaluation of thermal conductivity for sintered silver considering aging effect with microstructure based model" . | MICROELECTRONICS RELIABILITY 108 (2020) . |
| APA | Qin, Fei , Hu, Yuankun , Dai, Yanwei , An, Tong , Chen, Pei . Evaluation of thermal conductivity for sintered silver considering aging effect with microstructure based model . | MICROELECTRONICS RELIABILITY , 2020 , 108 . |
| 导入链接 | NoteExpress RIS BibTex |
摘要 ：
A six-side molded wafer-level chip scale package (mWLCSP) is a novel and attractive packaging method for smart phone applications due to its lower cost, better electrical performance, and higher long-term reliability. Nevertheless, wafer warpage in different manufacturing processes is a significant issue for the six-side mWLCSP. This article focuses on wafer warpage evolution in different packaging processes and the development of control method for the six-side mWLCSP. A quarter wafer-level finite-element (FE) model and a strip-level FE model were established to simulate the actual packaging processes by element birth and death method and restart technology. Both the FE models were proved quite efficient and accurate for warpage prediction compared to the experimental results. The effects of geometric parameters and material parameters on the maximum warpage value were studied based on the two established FE warpage models, and some recommendations were given for warpage optimization. Based on the above studies, an improved manufacturing process flow for the six-side mWLCSP was presented and proved feasible to control the maximum warpage value under 3 mm. It offers an insight work for the development and warpage control of the six-side mWLCSP and other wafer-level molded packages.
关键词 ：
Control Control Semiconductor device modeling Semiconductor device modeling wafer-level compression molding wafer-level compression molding Semiconductor device reliability Semiconductor device reliability Finite element analysis Finite element analysis Silicon Silicon six-side molded wafer-level chip scale package (mWLCSP) six-side molded wafer-level chip scale package (mWLCSP) finite-element method (FEM) finite-element method (FEM) warpage warpage Computational modeling Computational modeling Packaging Packaging
引用：
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| GB/T 7714 | Qin, Fei , Zhao, Shuai , Dai, Yanwei et al. Study of Warpage Evolution and Control for Six-Side Molded WLCSP in Different Packaging Processes [J]. | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY , 2020 , 10 (4) : 730-738 . |
| MLA | Qin, Fei et al. "Study of Warpage Evolution and Control for Six-Side Molded WLCSP in Different Packaging Processes" . | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY 10 . 4 (2020) : 730-738 . |
| APA | Qin, Fei , Zhao, Shuai , Dai, Yanwei , Yang, Mengke , Xiang, Min , Yu, Daquan . Study of Warpage Evolution and Control for Six-Side Molded WLCSP in Different Packaging Processes . | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY , 2020 , 10 (4) , 730-738 . |
| 导入链接 | NoteExpress RIS BibTex |
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